1. Field of the Invention
The present invention relates generally to a semiconductor memory device and a method of manufacturing the semiconductor memory device. More particularly, the invention relates to, for instance, a trench-capacitor DRAM.
2. Description of the Related Art
With a further shrink in DRAM (Dynamic Random Access Memory) cell size, the area of the capacitor has decreased more and more, and it is difficult to ensure a sufficient capacitance of the capacitor. In the situation, more importance is placed on technology wherein a high-dielectric-constant material such as Al2O3, TaO or BSTO is used for the capacitor insulation film of the cell capacitor, and a greater accumulation capacitance is ensured with the same pattern occupation area. In the case where a high-dielectric-constant film, which is typically a metal oxide, is applied to the trench-type cell, as mentioned above, it is necessary to bury a high-dielectric-constant material in the trench capacitor that is formed in the semiconductor substrate. In this case, it is imperative to reduce as much as possible the area at which the semiconductor substrate contacts the high-dielectric-constant film, and to provide the structure that prevents contact with the vicinity of the cell transistor, which may lead to cell leak. The reason is that if the high-dielectric-constant material included in the capacitor insulation film diffuses into the substrate, the diffused material would become a trap center, resulting in an increase in junction leakage current and degradation in retention characteristics.
In the conventional trench capacitor cell structure, which is generally called “BEST cell structure”, a storage node and a diffusion layer of each cell transistor are coupled within the substrate. Thereby, the trench capacitor and cell transistors are electrically connected. In this case, however, the high-dielectric-constant film, which is formed as the capacitor insulation film, and the diffusion layer of the cell transistor come in direct contact with each other. Alternatively, the high-dielectric-constant film and the diffusion layer of the cell transistor contact each other via a surface strap. Consequently, impurities in the high-dielectric-constant film may possibly diffuse into the junction region in the substrate or into the surface strap. Like the above-described case, a junction leak due to diffusion of the impurities will increase, and the retention characteristics may deteriorate. Hence, even in the case where the high-dielectric-constant film is applied to the BEST cell, it is necessary to solve the problem of the degradation in retention characteristics.
Normally, the BEST cell is fabricated by a step of forming an active area of a cell transistor, after the formation of a trench capacitor. Thus, a step of removing a side face portion of the trench capacitor along the active area is indispensable. In this case, the high-dielectric-constant film may possibly be exposed at the time of processing the active area, and the high-dielectric-constant impurities may re-adsorb. This may lead to deterioration in retention characteristics.
For instance, IEEE 2002 (H. Seidl et al., “A Fully Integrated Al2O3 Trench Capacitor DRAM For Sub-100 nm Technology”) proposes a technique for solving the above-described problem. In this technique, the following fabrication step is added. That is, after the processing of a trench, a high-dielectric-constant film is formed. Then, a storage node electrode of polysilicon is formed by deposition, and the storage node is recessed. Thereafter, the high-dielectric-constant film at the upper part of the trench is removed by wet etching.
In this technique, however, it is necessary to directly deposit the high-dielectric-constant film on the region that becomes a source or drain diffusion layer of the cell transistor. It is very difficult to sufficiently remove the impurities of the high-dielectric-constant material by wet etching, etc. Possible diffusion of residual impurities may degrade the retention characteristics of the DRAM cell. In general, Al2O3, used in the aforementioned document, requires sufficient anneal prior to formation of a storage node electrode. Although varying depending on the method of forming the Al2O3 film, when an atomic layer deposition (ALD) method that is widely used in recent years is applied, a great deal of excess Al-based or C-based impurities remains after the film formation. By annealing out such impurities, satisfactory film characteristics are obtained. If a storage node electrode is formed in the state in which annealing is insufficient, and a high-temperature, long-time heat treatment for the DRAM is carried out, the excess Al, that is P-type impurities, diffuses into the storage node electrode, depletes the surface of the storage node electrode and decreases the capacitance of the capacitor. Furthermore, it is very difficult to wet-etch the high-dielectric-constant material such as Al2O3 film, which is crystallized by adequate annealing. In the manufacturing method of the above-described document, there are problems of not only a decrease in retention characteristics, but also depletion of the storage node electrode due to the impurities.